Combinatorial processing provides high throughput evaluation of semiconductor processes and materials. The systems supporting the combinatorial processing are flexible to accommodate the demands for running the different processes either in parallel, serial or some combination of the two.
Some semiconductor wet processing operations include operations for adding (electro-depositions) and removing layers (etch), defining features, preparing layers (e.g., cleans), etc. Similar processing techniques apply to the manufacture of integrated circuits (IC) semiconductor devices, flat panel displays, optoelectronics devices, data storage devices, magneto electronic devices, magneto optic devices, packaged devices, and the like. As feature sizes continue to shrink, improvements, whether in materials, unit processes, or process sequences, are continually being sought for the deposition processes. However, semiconductor companies conduct R&D on full wafer processing through the use of split lots, as the deposition systems are designed to support this processing scheme. This approach has resulted in ever escalating R&D costs and the inability to conduct extensive experimentation in a timely and cost effective manner. Combinatorial processing as applied to semiconductor manufacturing operations enables multiple experiments to be performed on a single substrate.
During combinatorial experiments it is beneficial to provide as much flexibility as possible with regard to the tools performing the processing. In addition, the equipment for performing the combinatorial experiments should be designed to minimize particle generation. It is within this context that the embodiments arise.